EINT=0, AA=0, DINC=0, UMNSM=00, D_REQ=0, ERQ=0, SMOD=0000, START=0, EADREQ=0, LINKCC=00, LCH2=00, SSIZE=00, CS=0, DMOD=0000, DSIZE=00, SINC=0, LCH1=00
DMA Control Register
| LCH2 | Link Channel 2 0 (00): DMA Channel 0 1 (01): DMA Channel 1 2 (10): DMA Channel 2 3 (11): DMA Channel 3 |
| LCH1 | Link Channel 1 0 (00): DMA Channel 0 1 (01): DMA Channel 1 2 (10): DMA Channel 2 3 (11): DMA Channel 3 |
| LINKCC | Link Channel Control 0 (00): No channel-to-channel linking 1 (01): Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0. 2 (10): Perform a link to channel LCH1 after each cycle-steal transfer 3 (11): Perform a link to channel LCH1 after the BCR decrements to 0. |
| D_REQ | Disable Request 0 (0): ERQ bit is not affected. 1 (1): ERQ bit is cleared when the BCR is exhausted. |
| DMOD | Destination Address Modulo 0 (0000): Buffer disabled 1 (0001): Circular buffer size is 16 bytes 2 (0010): Circular buffer size is 32 bytes 3 (0011): Circular buffer size is 64 bytes 4 (0100): Circular buffer size is 128 bytes 5 (0101): Circular buffer size is 256 bytes 6 (0110): Circular buffer size is 512 bytes 7 (0111): Circular buffer size is 1 KB 8 (1000): Circular buffer size is 2 KB 9 (1001): Circular buffer size is 4 KB 10 (1010): Circular buffer size is 8 KB 11 (1011): Circular buffer size is 16 KB 12 (1100): Circular buffer size is 32 KB 13 (1101): Circular buffer size is 64 KB 14 (1110): Circular buffer size is 128 KB 15 (1111): Circular buffer size is 256 KB |
| SMOD | Source Address Modulo 0 (0000): Buffer disabled 1 (0001): Circular buffer size is 16 bytes. 2 (0010): Circular buffer size is 32 bytes. 3 (0011): Circular buffer size is 64 bytes. 4 (0100): Circular buffer size is 128 bytes. 5 (0101): Circular buffer size is 256 bytes. 6 (0110): Circular buffer size is 512 bytes. 7 (0111): Circular buffer size is 1 KB. 8 (1000): Circular buffer size is 2 KB. 9 (1001): Circular buffer size is 4 KB. 10 (1010): Circular buffer size is 8 KB. 11 (1011): Circular buffer size is 16 KB. 12 (1100): Circular buffer size is 32 KB. 13 (1101): Circular buffer size is 64 KB. 14 (1110): Circular buffer size is 128 KB. 15 (1111): Circular buffer size is 256 KB. |
| START | Start Transfer 0 (0): DMA inactive 1 (1): The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0. |
| DSIZE | Destination Size 0 (00): 32-bit 1 (01): 8-bit 2 (10): 16-bit 3 (11): Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) |
| DINC | Destination Increment 0 (0): No change to the DAR after a successful transfer. 1 (1): The DAR increments by 1, 2, 4 depending upon the size of the transfer. |
| SSIZE | Source Size 0 (00): 32-bit 1 (01): 8-bit 2 (10): 16-bit 3 (11): Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) |
| SINC | Source Increment 0 (0): No change to SAR after a successful transfer. 1 (1): The SAR increments by 1, 2, 4 as determined by the transfer size. |
| EADREQ | Enable asynchronous DMA requests 0 (0): Disabled 1 (1): Enabled |
| UMNSM | User Mode, Nonsecure Mode 0 (00): Channel attributes are set to the current mode. 1 (01): If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error. 2 (10): If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error. 3 (11): If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}. |
| CHACR | Channel Access Control |
| AA | Auto-align 0 (0): Auto-align disabled 1 (1): If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. |
| CS | Cycle Steal 0 (0): DMA continuously makes read/write transfers until the BCR decrements to 0. 1 (1): Forces a single read/write transfer per request. |
| ERQ | Enable Peripheral Request 0 (0): Peripheral request is ignored. 1 (1): Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled. |
| EINT | Enable Interrupt on Completion of Transfer 0 (0): No interrupt is generated. 1 (1): Interrupt signal is enabled. |